A solid state disk (SSD) may be implemented by using a NAND flash. The NAND flash is a non-volatile random access storage medium, and is characterized by that data does not disappear after poweroff. Before performing a re-write operation, the NAND flash needs to perform an erase operation first. Because a write operation uses page as a unit, an erase operation uses block as a unit, and a block needing to be erased may include a page into which valid data is written, the SSD may reserve some redundant area for data moving.
Movement of valid data requires a read control process and a write control process. In the read control process, a control chip reads valid data in a valid page in a source block to a read buffer. An error correcting code unit (ECU) performs error correcting code (ECC) checking on the valid data. In the ECC checking process, the valid data is decoded, data that passes the check and is decoded is written into a double data rate synchronous dynamic random access memory (DDR) through a direct memory access (DMA) data path. In the write control process, the control chip reads the decoded data from the DDR, sends, through the DMA data path, the data to the ECU for ECC coding, and writes coded valid data to a write buffer; and then, the write buffer writes the data into a blank block of the SSD.
To sum up, in a process of data moving in an existing SSD, the SSD needs to preempt back-end ECU resources, DDR resources, DMA data path resources, and CPU resources, and the like with a host, thereby degrading performance of the SSD.